A processing element architecture for high-density focal plane analog programmable array processors

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages

  Linan Cembrano G ^a   Espejo, S ^a   Dominguez Castro R ^a   Rodriguez Vazquez A ^a  

^a CSIC   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONVOLUTION; DATA COMMUNICATION EQUIPMENT; LINEAR NETWORKS; PARALLEL PROCESSING SYSTEMS;

ANALOG ARRAY PROCESSORS; DATA FLOW VISION ALGORITHM; PROCESSING ELEMENT ARCHITECTURE; PROGRAMMABLE ARRAY PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0036292426     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Vertical interactions across ten parallel, stacked representations in the mammalian retina
2. ACE16K: An advanced focal-plane analog programmable array processor
3. A pixel-parallel image processor using logic pitch-matched to dynamic memory
4. A programmable focal-plane analogue processor array
5. A mixed signal array processor with early vision applications
6. Design of programmable vision chips with low power consumption levels
7. Cellular neural networks: Theory
8. A 0.5um CMOS analog random access memory chip for teraOPS speed multimedia video processing