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European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 201-204

ACE16K: An advanced focal-plane analog programmable array processor

(4) Linan, G a Dominguez Castro, R a Espejo, S a Rodriguez Vazquez, A a

a CSIC (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DATA INTERCHANGE; FOCAL PLANES; LOW-POWER CONSUMPTION; PEAK VALUES; REAL-TIME IMAGE PROCESSING; SYSTEM LEVELS;

CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS;

IMAGE PROCESSING;

EID: 84893710661 PISSN: 19308833 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (19)

References (10)

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2
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3
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- C. Koch, H. Li (Eds.), Vision Chips, Implementing Vision Algorithms with Analog VLSI Circuits, IEEE Press, 1995.
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- Koch, C.¹ Li, H.²

4
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- Kluwer Academic Publishers
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- (2000) Vision Chips
- Moini, A.¹

5
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- John Wiley & Sons Ltd
- T. Roska and A. Rodríguez-Vázquez (Editors), Towards the Visual Microprocessor. John Wiley & Sons Ltd., 2000.
- (2000) Towards the Visual Microprocessor
- Roska, T.¹ Rodríguez-Vázquez, A.²

6
- 0037857497
- A 0.5m CMOS 106 transistors analog programmable array processor for real-time image processing
- Duisburg-Germany Sept
- G. Liñán, P. Foldesy, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez. "A 0.5m CMOS 106 Transistors Analog Programmable Array Processor for Real-Time Image Processing", Proc. of the 25th European Solid-State Circuits Conference, pp. 358-36, Duisburg-Germany, Sept. 1999.
- (1999) Proc. of the 25th European Solid-State Circuits Conference , pp. 358-436
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7
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- http://www.anafocus.com

8
- 0031188728
- A 0.8m CMOS programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
- July
- R. Domínguez-Castro, S. Espejo, A. Rodríguez- Vázquez, R. Carmona, P. Foldesy, A. Zarándy, P. Szolgay, T. Sziranyi and T. Roska, "A 0.8 m CMOS Programmable Mixed-Signal Focal-Plane Array Processor with On-Chip Binary Imaging and Instructions Storage", IEEE Journal of Solid State Circuits, Vol. 32, No. 7, pp. 1013-1026, July 1997.
- (1997) IEEE Journal of Solid State Circuits , vol.32 , Issue.7 , pp. 1013-1026
- Domínguez-Castro, R.¹ Espejo, S.² Rodríguez-Vázquez, A.³ Carmona, R.⁴ Foldesy, P.⁵ Zarándy, A.⁶ Szolgay, P.⁷ Sziranyi, T.⁸ Roska, T.⁹

9
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- Minimum size 0.5m CMOS programmable 48 x 48 CNN test chip
- Budapest, Hungary, September
- A. Paasio, A. Dawidziuk, K. Halonen andV. Porra, "Minimum Size 0.5m CMOS Programmable 48 x 48 CNN Test Chip", Proc. of the 1997 European Conference on Circuit Theory and Design, pp. 154-156, Budapest, Hungary, September 1997.
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10
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.