Lead-free wafer level-chip scale package: Assembly and reliability

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 1355-1358

  Patwardhan, V ^a   Kelkar, N ^a   Nguyen, L ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

WAFER LEVEL PACKAGE (WLP);

ELECTRONIC EQUIPMENT MANUFACTURE; EUTECTICS; RELIABILITY THEORY; SOLDERING; SURFACE MOUNT TECHNOLOGY;

CHIP SCALE PACKAGES;

EID: 0036290995     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2002.1008282     Document Type: Conference Paper

References (4)

1. A structured approach to lead-free IC assembly transitioning
2. Wafer level packaging has arrived
3. Wafer level chip scale packaging - Solder joint reliability
4. Micro SMD - A wafer level chip scale package