Wafer-level packaging has arrived

Semiconductor International

Volumn 23, Issue 12, 2000, Pages

  Garrou, Philip ^a,b,c  

^a IEEE

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

^c Dow Chemical's Adv Electron Mat ^*

Author keywords

[No Author keywords available]

Indexed keywords

DIE SINGULATION; INTEGRATED PASSIVE RADIO FREQUENCY COMPONENT; REDISTRIBUTION TECHNOLOGY; WAFER LEVEL PACKAGING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE TESTING; SILICON WAFERS; SOLDERING; SURFACE MOUNT TECHNOLOGY; THIN FILMS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 6744247095     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. P. Garrou, "Wafer Level Chip Scale Packaging: An Overview," IEEE Trans. Adv. Packaging, Vol. 23, 2000, p. 198.
2. Y. Tsukada, S. Tsuchida, Y. Nashimoto, "Surface Laminar Circuit and Flip Chip Attach Packaging," Proceedings Int. Microelectronics Conf., Yokohama, 1992, p. 252.
3. www.cyclotene.com
4. J. Wu, R. Pike, C.P. Wong, D.Scheck, W. Rogers, P. Garrou. "Evaluation of the Environmental Protection of Photo BCB Polymers," Proceed. Int. Symp. Adv. Packaging Materials, Atlanta, 2000, p. 90.
5. T. Kawahara, "Super CSP," IEEE Trans. Adv. Packaging, Vol. 23, 2000, p. 215.
6. A. Badihi et al, "A CSP Optoelectronic Package for Imaging and Light Detection Applications," Proc. IMAPS Conf., Tel Aviv, 1998, p. 1.
7. M. Toepper, J. Simon and H. Reichl "Redistribution Technology for Chip Scale Package Using Photo-BCB," Future Fab Int., 1996, p. 363.
8. M. Toepper et al, "Fab Integrated Packaging (FIP): A New Concept for High Reliability Wafer-Level Chip Size Packaging," Proceed. 50th Electronic Component Technology Conf., Las Vegas. 2000, p. 74.
9. N. Kelkar, R. Mathew, H Takiar, L. Nguyen, "MicroSMD - A Wafer Lever Chip Scale Package," IEEE Trans. Adv. Packaging, Vol. 23, 2000, p. 227.