A structured approach to lead-free IC assembly transitioning

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2002, Pages 215-222

  Nguyen, L ^a   Walberg, R ^a   Lin, Z ^b   Koh, T ^b   Bong, Y Y ^c   Chua, M C ^c   Yeoh, J J ^c  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b National Semiconductor   (Singapore)

^c National Semiconductor (M)   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; HIGH TEMPERATURE PROPERTIES; INTEGRATED CIRCUIT MANUFACTURE; RELIABILITY; SURFACE MOUNT TECHNOLOGY; TIN ALLOYS;

INTEGRATED CIRCUIT ASSEMBLY TRANSITIONING; SEMICONDUCTOR PACKAGING PRODUCTION; SOLDER BALLS;

ELECTRONICS PACKAGING;

EID: 0036395478     PISSN: 10898190     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEMT.2002.1032758     Document Type: Article

References (8)

1. PC Works 1999, October 23-28, 1999, Minneapolis, MN
2. IPC Works 2000, September 9-14, 2000, Miami, FL
3. IPC/JEDEC Int. Conf. On Lead-Free: Electronic Components and Assemblies, May 1-2, 2002, San Jose, CA.
4. "Lead-Free-Fantasy or Fact", MEPTEC 2000, June 14, 2000, Sunnyvale, CA
5. "Summit on Lead-Free Solder Implementation," MEPTEC 2001, January 10, 2001, San Jose, CA
6. "Lead-Free Solder Implementation Summit," MEPTEC 2001, August 30, 2001, Sunnyvale, CA.
7. Patwardhan, V., Nguyen, L., and Kelkar, N., "Lead-Free Wafer Level Chip Scale Package: Assembly and Reliability," 52nd Electron. Comp. & Tech. Conf., May 28-31, San Diego, CA (2002).
8. Hunt, C., "An Assessment of Lead-Free Palladium-Finished Components: The Impact on Assembly Yields with Conventional Tin/Lead Solder," Proc. IPC Works 2000, p. S-02-2, Miami, FL (2000).