The effect of via size on fine pitch and high density solder bumps for wafer level packaging

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 1178-1181

  Ju, Chul Won ^a   Kim, Seong Jin ^a   Pack, Kyu Ha ^a   Lee, Hee Tae ^a   Hyun, Young Chul ^a   Park, Seong Su ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; ELECTROPLATING; PHOTOLITHOGRAPHY; PHOTORESISTS; SILICON WAFERS; SPUTTERING;

SOLDER BUMPS;

ELECTRONICS PACKAGING;

EID: 0036290896     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Solder bump fabri-cation on wafers by electroplating process
2. Reliability testing and stress strain estimations of flip-chip joints made by stud-bumpbonding technique
3. Bumping of silicon wafers by stencil printing
4. Stencil printing process development for low cost flip chip interconnect
5. Solder-jetted eutectic PbSn bumps for flip-chip
6. Transcription solder bump technology using the evaporation method