Stencil printing process development for low cost flip chip interconnect

Proceedings - Electronic Components and Technology Conference

Volumn Part F133492, Issue , 1998, Pages 421-426

  Li, Li ^a   Wiegele, S ^a   Thompson, P ^a   Lee, R ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRIDGES; COSTS; DEPOSITS; DESIGN OF EXPERIMENTS; ELECTRONICS PACKAGING; EUTECTICS; INTEGRATED CIRCUIT INTERCONNECTS; NETWORK COMPONENTS; PHOTORESISTS; RELIABILITY ANALYSIS; SOLDERING; SOLDERING ALLOYS; COST EFFECTIVENESS; ELECTROLESS PLATING; GOLD; INTEGRATED CIRCUIT MANUFACTURE; MASKS; METALLOGRAPHIC MICROSTRUCTURE; NICKEL; SCANNING ELECTRON MICROSCOPY; STATISTICAL METHODS;

COST-SENSITIVE APPLICATIONS; FLIP-CHIP INTERCONNECTION; INTERCONNECT RELIABILITY; MICROSTRUCTURE ANALYSIS; PROCESS PARAMETER OPTIMIZATION; RELIABILITY REQUIREMENTS; SOLDER PASTE SELECTIONS; UNDER-BUMP METALLURGIES;

FLIP CHIP DEVICES;

STENCIL PRINTING PROCESS; UNDER BUMP METALLURGY (UBM); WAFER SOLDER BUMPING;

EID: 0031619645     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.1998.678728     Document Type: Conference Paper

References (4)

1. Greer, S. E. "An Extended Eutectic Solder Bump for FCOB", Proc 46' Electronic Components and Technology Conf, Orlando, FL, May. 1996, pp. 546-551.
2. Xiao, M., Lawless, K. L., Lee, N., "Prospects of Solder Paste Application in Ultra Fine Pitch Era", Proceedings of Surface Mount International, San Jose, CA, Sept. 1993, pp. 454-468.
3. Pfeifer, M. "Solder Bump Size and Shape Modeling and Experiment Validation", IEEE Trans-CPMT-B, Vol. 20, No. 4 (1997), pp. 452-457.
4. Wiegele, S., Thompson, P., et al., "Reliability and Process Characterization of Electroless Nickel-Gold Solder Flip Chip Interconnect Technology", To be published in Proc 48 Electronic Components and Technology Conf, Seattle, WA. May. 1998.