Model to hardware correlation for power distribution induced I/O noise in a functioning computer system

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 319-324

  Chun, Sungjun ^a   Smith, Larry ^b   Anderson, Ray ^b   Swaminathan, Madhavan ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS; DIELECTRIC MATERIALS; ELECTRIC LINES; ELECTRIC POTENTIAL; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE; WAVEFORM ANALYSIS;

POWER DISTRIBUTION SYSTEMS (PDS);

ELECTRIC POWER DISTRIBUTION;

EID: 0036290636     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2002.1008114     Document Type: Article

References (10)

1. Comparison of mesh and solid planes for use in electrical packaging
2. Simultaneous switch noise and power plane bounce for CMOS technology
3. Modeling of simultaneous switching noise in high speed systems
4. Distributed SPICE circuit model for ceramic capacitors
5. Power distribution system design methodology and capacitor selection for modern CMOS technology
6. Lossy power distribution networks with thin dielectric layers and/or thin conductive layers
7. Power plane SPICE models and simulated performance for materials and geometries