A robust self-resetting CMOS 32-bit parallel adder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages 473-476

  Jung, Gunok ^a   Sundarajan, Venkat ^a   Sobelman, Gerald E ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BOOLEAN FUNCTIONS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; SEMICONDUCTOR DEVICE STRUCTURES; THERMAL EFFECTS;

32-BIT PARALLEL ADDER; DUAL-RAIL DOMINO CIRCUIT; SELF-RESETTING CMOS;

CMOS INTEGRATED CIRCUITS;

EID: 0036287183     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1009880     Document Type: Article

References (8)

1. Skew-tolerant domino circuits
2. Time borrowing in high-speed functional units using skew-tolerant domino circuits
3. High-speed adder design using time borrowing and early carry propagation
4. Implementation of a self-resetting CMOS 64-Bit parallel adder with enhanced testability
5. Optimal clocking and enhanced testability for high-performance self-resetting domino pipelines
6. Self-timed rings and their application to division
7. Custom circuit design as a driver of microprocessor performance