Design verification using formal techniques

International Conference on ASIC, Proceedings

Volumn , Issue , 2001, Pages 21-28

  Zhu, Yunshan ^a   Marshall, Tom ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; FORMAL LOGIC;

BOOLEAN EQUIVALENCE CHECKING; DESIGN VERIFICATION; FORMAL VERIFICATION; FUNCTIONAL VERIFICATION; UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER;

LOGIC DESIGN;

EID: 0035721335     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (20)

1. Nuts and bolts of core and SoC verification
2. Validating the intel pentium 4 microprocessor
3. Verifying sequential behavior with model checking
4. Semi-formal test generation with genevieve
5. Temporal and modal logic
6. Methodology and case studies
7. Smart simulation using collaborative formal and simulation engines
8. Symbolic rtl simulation
9. Equivalence checking using cuts and heaps
10. A compositional rule for hardware design refinement
11. Commercial design verification: Methodology and tools
12. Anatomy of the Pentium bug
13. Designware foundation library databook