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Volumn , Issue , 1996, Pages 839-848
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Commercial design verification: Methodology and tools
a
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Author keywords
[No Author keywords available]
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Indexed keywords
INTEGRATED CIRCUIT TESTING;
SEMICONDUCTOR DEVICE MODELS;
INTEGRATED CIRCUIT DESIGN VERIFICATION;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0030389594
PISSN: 10893539
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (18)
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References (24)
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