Method of generating tests for marginal delays and delay faults in combinational circuits

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 320-325

  Takahashi, Hiroshi ^a   Matsunaga, Toshiyuki ^a   Boateng, Kwame Osei ^a   Takamatsu, Yuzo ^a  

^a EHIME UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MARGINAL DELAYS (MD);

ALGORITHMS; COMBINATORIAL CIRCUITS; LOGIC GATES; SEMICONDUCTOR DEVICE MODELS;

INTEGRATED CIRCUIT TESTING;

EID: 0031362115     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. A. Chatterjee and J. A. Abraham, "RAFT:A Novel Program for Rapid-Fire Test and Diagnosis of Digital Logic for Marginal Delays and Delay Faults", Proc. ICCAD, pp.340-343, 1994.
2. Z.Barzilai and B.K.Rosen, "Comparison of AC Self-testing Procedures ", Proc. ITC, pp.89-94, Oct. 1983.
3. G.L. Smith, "Model for Delay Faults Based upon Paths", Proc. ITC. pp.342-349, 1985.
4. A.K. Pramanick and S.M. Reddy, "On the Detection of Delay Faults", Proc. ITC, pp.845-856, 1988.
5. E.S. Park and M.R. Mercer, "An Efficient Delay Test Generation System for Combinational Logic Circuits", Proc. DAC, pp.522-528, 1990.
6. U. Mahlstedt, "DEUTEST: Deterministic Test Generation for Gate Delay Faults", Proc. ITC, pp.972-980, 1993.
7. V.S. Iyengar, B.K. Rosen and I. Spillinger, "Delay Test Generation", Proc. ITC, pp.857-866, 1988.
8. W-W. Mao and M.D. Ciletti, "A Variable Observation Time Method for Testing Delay Faults", Proc. 27th DAC, pp.728-731, June 1990.
9. H. Takahashi, T. Watanabe and Y. Takamatsu, "Generation of Tenacious Tests for Small Gate Delay Faults in Combinational Circuits", Proc. ATS'95, pp.332-338, Nov. 1995.
10. N. Itazaki, Y. Idomoto and K. Kinoshita, "A Fault Simulation Method for Crosstalk Faults in Sequential Circuits", Proc. FTCS-26, pp.38-43, June 1996.