BIST approach for very deep sub-micron (VDSM) defects

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 283-291

  Sato, Yasuo ^a   Ikeya, Toyohito ^a   Nakao, Michinobu ^a   Nagumo, Takaharu ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; DEFECTS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING;

PATTERN QUALITY; SCAN PATTERNS; VERY DEEP SUBMICRON;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0034481608     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)