Multi-ring active analogic protection for minority carrier injection suppression in Smart Power technology

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2001, Pages 351-354

  Gonnard, O ^a   Charitat, G ^a   Lance, Ph ^a   Suquet, M ^a   Bafleur, M ^a   Laine, J P ^a   Peyre Lavigne, A ^a  

^a LAAS CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CROSSTALK; CURRENT DENSITY; ELECTRIC FIELD EFFECTS; ELECTRIC RESISTANCE; INDUCED CURRENTS;

SMART POWER TECHNOLOGY;

SEMICONDUCTOR DEVICES;

EID: 0034823068     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Recent ESD studies in Smartmos technologies
2. DC substrate coupling between LDMOS and CMOS devices in hyper-integration I technology
3. A novel cross-talk isolation structure for bulk CMOS power IC's
4. Design model and guideline for n-well guard ring in epitaxial CMOS
5. Smart power approaches VLSI complexity
6. Substrate current protection in smart power IC's
7. Suppression of substrate injection by RESURF LDMOS devices in a smart power technology for 20-30V applications
8. Substrate crosstalk reduction using SOI technology