Tester retargetable patterns

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 721-727

  Kapur, Rohit ^a   Williams, T W ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DESIGN FOR TESTABILITY; MICROPROCESSOR CHIPS;

TESTER RETARGETABLE PATTERNS;

INTEGRATED CIRCUIT TESTING;

EID: 0035681197     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966693     Document Type: Article

References (11)

1. An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing
2. Inductive fault analysis of MOS integrated circuits
3. Test vector compression via cyclical scan chains and its application to testing core based designs
4. A pattern skipping method for weighted random pattern testing
5. Test point insertion for compact test sets
6. rd generation coldfire family of microprocessors
7. Low cost testing of high density logic components
8. Standard test interface language (STIL): A new language for patterns and waveforms