Partial scan design methods based on internally balanced structure

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1998, Pages 211-216

  Takasaki, Tomoya ^a   Inoue, Tomoo ^a   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; FLIP FLOP CIRCUITS; SEMICONDUCTOR DEVICE STRUCTURES; SEQUENTIAL CIRCUITS;

BYPASS FLIP FLOPS; INTERNALLY BALANCED STRUCTURES; PARTIAL SCAN DESIGN METHODS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032218683     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (14)