On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 211-220

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^b  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; SEQUENTIAL CIRCUITS; TIMING CIRCUITS; VECTORS; VLSI CIRCUITS;

FUNCTIONAL TEST SEQUENCES;

INTEGRATED CIRCUIT TESTING;

EID: 0035680669     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966636     Document Type: Article

References (13)

1. IDDQ and AC scan: The War against unmodelled defects
2. A design for testability scheme to reduce test application time in full scan
3. An algorithm to reduce test application time in full scan designs
4. Test application time reduction for sequential circuits with scan
5. Static test compaction for scan-based designs to reduce test application time
6. Selected length partial scan: A method to reduce vector length
7. Overall consideration of scan design and test generation
8. Reduced scan shift: A new testing method for sequential circuits
9. Test time reduction in scan designed circuits
10. A serial scan test vector compression methodology
11. Sequential circuit test generation using dynamic state traversal
12. Vector restoration based static compaction of test sequences for synchronous sequential circuits
13. Proptest: A property based test pattern generator for sequential circuits using test compaction