-
2
-
-
0021505260
-
A CMOS floating point multiplier
-
Oct.
-
J. Uya, K. Kaneko, and J. Yasui, "A CMOS floating point multiplier," IEEE J. Solid-State Circuits, vol. SC-19, pp. 697-702, Oct. 1984.
-
(1984)
IEEE J. Solid-State Circuits
, vol.SC-19
, pp. 697-702
-
-
Uya, J.1
Kaneko, K.2
Yasui, J.3
-
4
-
-
84937349985
-
High-speed arithmetic in binary computers
-
O. L. MacSorley, "High-speed arithmetic in binary computers," Proc. IRE, vol. 49, pp. 67-91, 1961.
-
(1961)
Proc. IRE
, vol.49
, pp. 67-91
-
-
MacSorley, O.L.1
-
5
-
-
0020102009
-
A regular layout for parallel adders
-
Mar.
-
R. P. Brent and H. T. Kung, "A regular layout for parallel adders," IEEE Trans. Comput., vol. C-31, pp. 260-264, Mar. 1982.
-
(1982)
IEEE Trans. Comput.
, vol.C-31
, pp. 260-264
-
-
Brent, R.P.1
Kung, H.T.2
-
6
-
-
0026173205
-
Delay optimization of carry-skip adders and block carry-lookahead adders
-
P. K. Chan, M. D. F. Schlag, C. D. Thomborson, and V. G. Oklobdzija, "Delay optimization of carry-skip adders and block carry-lookahead adders," in Proc. 10th Comput. Arithmetic Symp., 1991, pp. 154-164.
-
(1991)
Proc.
, vol.10
, pp. 154-164
-
-
Chan, P.K.1
Schlag, M.D.F.2
Thomborson, C.D.3
Oklobdzija, V.G.4
-
8
-
-
84937351672
-
Skip techniques for high-speed carry propagation in binary arithmetic units
-
Dec.
-
M. Lehman and N. Burla, "Skip techniques for high-speed carry propagation in binary arithmetic units," IRE Trans. Electron. Comput., vol. EC-10, pp. 691-698, Dec. 1962.
-
(1962)
IRE Trans. Electron. Comput.
, vol.EC-10
, pp. 691-698
-
-
Lehman, M.1
Burla, N.2
-
9
-
-
0024917242
-
Optimal group distribution in carry-skip adders
-
S. Turrini, "Optimal group distribution in carry-skip adders," in Proc. 9th Comput. Arithmetic Symp., 1989, pp. 96-103.
-
(1989)
Proc. 9th Comput. Arithmetic Symp.
, pp. 96-103
-
-
Turrini, S.1
-
10
-
-
84913396280
-
Conditional-sum addition logic
-
June
-
J. Sklansky, "Conditional-sum addition logic," IRE Trans. Electron. Comput., vol. EC-9, pp. 226-231, June 1960.
-
(1960)
IRE Trans. Electron. Comput.
, vol.EC-9
, pp. 226-231
-
-
Sklansky, J.1
-
12
-
-
84937078021
-
Signed digit number representation for fast parallel arithmetic
-
Sept.
-
A. Avizienis, "Signed digit number representation for fast parallel arithmetic," IRE Trans. Comput., vol. EC-10, pp. 389-400, Sept. 1961.
-
(1961)
IRE Trans. Comput.
, vol.EC-10
, pp. 389-400
-
-
Avizienis, A.1
-
14
-
-
0029369866
-
Fast two's complement VLSI adder design
-
Sept. 28
-
J. M. Dobson and G. M. Blair, "Fast two's complement VLSI adder design," Electron. Lett., vol. 31, no. 20, pp. 773-783, Sept. 28, 1995.
-
(1995)
Electron. Lett.
, vol.31
, Issue.20
, pp. 773-783
-
-
Dobson, J.M.1
Blair, G.M.2
-
15
-
-
0030169609
-
An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture
-
June
-
H. Makino et al., "An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture," IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 773-783, June 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.6
, pp. 773-783
-
-
Makino, H.1
-
16
-
-
0031347824
-
Fast Binary Addition
-
Leicester, U.K., Nov.
-
K. K. Parhi, "Fast Binary Addition," in Proc. IEEE Signal Processing Syst., Leicester, U.K., Nov. 1997, pp. 232-241.
-
(1997)
Proc. IEEE Signal Processing Syst.
, pp. 232-241
-
-
Parhi, K.K.1
-
17
-
-
33747830314
-
Fast low-power VLSI binary addition
-
Austin, TX, Oct.
-
_, "Fast low-power VLSI binary addition," in Proc. IEEE Int. Conf. Comput. Design, Austin, TX, Oct. 1997, pp. 676-684.
-
(1997)
Proc. IEEE Int. Conf. Comput. Design
, pp. 676-684
-
-
-
18
-
-
0030264539
-
Area-time-power tradeoffs in parallel adders
-
Oct.
-
C. Nagendra, M. J. Irwin, and R. M. Owens, "Area-time-power tradeoffs in parallel adders," IEEE Trans. Circuits Syst. II, vol. 43, pp. 689-702, Oct. 1996.
-
(1996)
IEEE Trans. Circuits Syst. II
, vol.43
, pp. 689-702
-
-
Nagendra, C.1
Irwin, M.J.2
Owens, R.M.3
-
19
-
-
0030407484
-
Estimation of average consumption of ripple-carry adder based on average length carry chains
-
San Francisco, CA, Oct. 30-Nov. 1
-
L. Montalvo, K. K. Parhi, and J. H. Satyanarayana, "Estimation of average consumption of ripple-carry adder based on average length carry chains," in Proc. IEEE Workshop VLSI Signal Processing IX, San Francisco, CA, Oct. 30-Nov. 1, 1996, pp. 189-198.
-
(1996)
Proc. IEEE Workshop VLSI Signal Processing IX
, pp. 189-198
-
-
Montalvo, L.1
Parhi, K.K.2
Satyanarayana, J.H.3
-
20
-
-
0002751923
-
Low-power arithmetic components
-
J. M. Rabaey and M. Pedram, Eds. Norwell, MA: Kluwer
-
T. K. Callaway and E. E. Swartzlander, "Low-power arithmetic components," in Low-Power Design Methodologies, J. M. Rabaey and M. Pedram, Eds. Norwell, MA: Kluwer, 1996, pp. 161-200.
-
(1996)
Low-Power Design Methodologies
, pp. 161-200
-
-
Callaway, T.K.1
Swartzlander, E.E.2
-
21
-
-
0029293575
-
Minimizing power consumption in digital CMOS circuits
-
Apr.
-
A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, pp. 498-523, Apr. 1995.
-
(1995)
Proc. IEEE
, vol.83
, pp. 498-523
-
-
Chandrakasan, A.P.1
Brodersen, R.W.2
-
22
-
-
0029214519
-
Sign detection and comparison networks with a small number of transitions
-
Bath, U.K., July
-
M. D. Ercegovac and T. Lang, "Sign detection and comparison networks with a small number of transitions," in Proc. 12th Comput. Arithmetic Symp., Bath, U.K., July 1995, pp. 59-66.
-
(1995)
Proc.
, vol.12
, pp. 59-66
-
-
Ercegovac, M.D.1
Lang, T.2
-
23
-
-
0029717574
-
HEAT: Hierarchical energy analysis tool
-
Las Vegas, NV, June
-
J. H. Satyanarayana and K. K. Parhi, "HEAT: Hierarchical energy analysis tool," in 33rd ACM/IEE Design Automation Conf., Las Vegas, NV, June 1996, pp. 9-14.
-
(1996)
33rd ACM/IEE Design Automation Conf.
, pp. 9-14
-
-
Satyanarayana, J.H.1
Parhi, K.K.2
-
24
-
-
0025448597
-
A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor
-
June
-
A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer, and P. G. A. Jespers, "A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor," IEEE J. Solid-State Circuits, vol. 25, pp. 748-756, June 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 748-756
-
-
Vandemeulebroecke, A.1
Vanzieleghem, E.2
Denayer, T.3
Jespers, P.G.A.4
-
25
-
-
0015651305
-
A parallel algorithm for the efficient solution of a general class of recurrence equations
-
Aug.
-
P. M. Kogge and H. S. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations," IEEE Trans. Comput., vol. C-22, pp. 786-792, Aug. 1973.
-
(1973)
IEEE Trans. Comput.
, vol.C-22
, pp. 786-792
-
-
Kogge, P.M.1
Stone, H.S.2
-
26
-
-
0024700229
-
Pipeline interleaving and parallelism in recursive digital filters: Parts I and II
-
July
-
K. K. Parhi and D. G. Messerschmitt, "Pipeline interleaving and parallelism in recursive digital filters: Parts I and II," IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1099-1135, July 1989.
-
(1989)
IEEE Trans. Acoust., Speech, Signal Processing
, vol.37
, pp. 1099-1135
-
-
Parhi, K.K.1
Messerschmitt, D.G.2
|