Designing a modern memory hierarchy with hardware prefetching

IEEE Transactions on Computers

Volumn 50, Issue 11, 2001, Pages 1202-1218

  Lin, Wei Fen ^a,c   Reinhardt, Steven K ^c,d   Burger, Doug Burger ^d  

^a IEEE   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

^d NONE

Author keywords

Caches; Memory bandwidth; Memory system design; Prefetching; Rambus DRAM; Spatial locality

Indexed keywords

BANDWIDTH; CACHE MEMORY; MICROPROCESSOR CHIPS; OPTIMIZATION; QUEUEING NETWORKS; TIMING CIRCUITS;

HARDWARE PREFETCHING; MEMORY SYSTEM DESIGN;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035510681     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.966495     Document Type: Article

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