BIST TPGs for faults in board level interconnect via boundary scan

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 376-382

  Chiang, Chen Huan ^a   Gupta, Sandeep K ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; ELECTRONICS PACKAGING; INTERCONNECTION NETWORKS;

BOUNDARY SCAN ARCHITECTURE; BUILT IN SELF TEST (BIST); TEST PATTERN GENERATOR;

INTEGRATED CIRCUIT TESTING;

EID: 0030712696     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)