The 2.4F2 memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM

2000 International Conference on Modeling and Simulation of Microsystems - MSM 2000

Volumn , Issue , 2000, Pages 388-391

  Suzuki, Masahiko ^a   Endoh, Tetsuo ^a   Sakuraba, Hiroshi ^a   Masuoka, Fujio ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

DRAM; S SGT; SGT; Three dimensional memory

Indexed keywords

CAPACITORS; COMPUTER SIMULATION; DIELECTRIC MATERIALS; PARAMETER ESTIMATION; SEMICONDUCTOR JUNCTIONS; THICKNESS MEASUREMENT;

MEMORY CELLS; STACKED SURROUNDING GATE TRANSISTOR (SGT); STACKING CELLS; THREE DIMENSIONAL MEMORY;

GATES (TRANSISTOR);

EID: 0004393223     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. T. Hasegawa, D. Takashima, R. Ogiwara, M. Ohta, S. Shiratake, T. Hamamoto, T. Yamada, M. Aoki, S. Ishibashi, Y. Oowaki, S. Watanabe and F. Masuoka, "An Experimental DRAM with a NAND-Structured Cell", IEEE Journal of Solid-State Circuits, Vol. 28, pp.1099-1104, 1993.
3. T. Endoh, K. Shinmei, H. Sakuraba and F. Masuoka, "The analysis of the stacked-surrounding gate transistor (S-SGT) DRAM for the high speed and low voltage operation", IEICE Trans. Electron., vol. E81-C, No.9, p. 1491, 1998.
4. T. Endoh, K. Shinmei, H. Sakuraba and F. Masuoka, "New Three-Dimensional Memory Array Architecture for Future Ultrahigh-Density DRAM", IEEE J. Solid-State Circuits, vol. 34, No.4, pp. 476-483, 1999.
5. T. Endoh, K. Shinmei and F. Masuoka, "The Stacked-SGT DRAM using 3D-building memory array technology", Trans. Inst. Electron. Inf. Commun. Eng. Jpn., vol. J81-C-I, No.5, p. 288, 1998.
6. 2 Memory Cell Technology with Stacked-Surrounding Gate Transistor (S-SGT) DRAM", Trans. Inst. Electron. Inf. Commun. Eng. Jpn., to be published.