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Volumn 41, Issue 7, 2001, Pages 1045-1048
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Sub-100 nm CMOS circuit performance with high-K gate dielectrics
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Author keywords
[No Author keywords available]
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Indexed keywords
CAPACITANCE;
COMPUTER SIMULATION;
DIELECTRIC MATERIALS;
GATES (TRANSISTOR);
INTEGRATED CIRCUIT TESTING;
MONTE CARLO METHODS;
SILICA;
FRINGING CAPACITANCE;
CMOS INTEGRATED CIRCUITS;
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EID: 0035394420
PISSN: 00262714
EISSN: None
Source Type: Journal
DOI: 10.1016/S0026-2714(01)00068-3 Document Type: Article |
Times cited : (3)
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References (6)
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