A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 6, 2001, Pages 944-955

  Park, Yong Ha ^a   Han, Seon Ho ^b   Lee, Jung Hwan ^c   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^c Hynix Semiconductor Inc   (South Korea)

Author keywords

3 D graphic rendering; Embedded logic; Embedded memory

Indexed keywords

BANDWIDTH; LOGIC CIRCUITS; MAPPING; MULTIMEDIA SYSTEMS; RANDOM ACCESS STORAGE;

EMBEDDED LOGIC; EMBEDDED MEMORY; HIERARCHICAL OCTET TREE;

CMOS INTEGRATED CIRCUITS;

EID: 0035368865     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.924857     Document Type: Article

References (18)

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