A 7.1GB/s low-power 3D rendering engine in 2D array-embedded memory logic CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 242-243

  Park, Y H ^a   Han, S H ^a   Kim, J S ^a   Lee, S J ^a   Kook, J H ^a   Lim, J W ^a   Woo, R ^a   Yoo, H J ^a   Lee, J H ^a,a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; EMBEDDED SYSTEMS; INTERPOLATION; PARALLEL PROCESSING SYSTEMS; THREE DIMENSIONAL COMPUTER GRAPHICS; THROUGHPUT;

EMBEDDED MEMORY LOGIC (EML); RENDERING ENGINES;

CMOS INTEGRATED CIRCUITS;

EID: 0034428845     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Implementing application specific memory
2. Intelligent RAM (IRAM): Chip that remember and compute
3. A 10Mb 3D frame buffer memory with Z-compare and alpha blending
4. A 7.68GIPS 3.84GB/s 1W parallel image-processing RAM integrating a 16Mb DRAM and 128 processor
5. A modular architecture for a 6.4GB/s, 8Mb DRAM-integrated media chip
6. A 30ns 256Mb DRAM with multi-divided array structure