A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 5, 1997, Pages 635-640

  Watanabe, Takao ^a,b   Fujita, Ryo ^b,c,d   Yanagisawa, Kazumasa ^b,e,f   Tanaka, Hitoshi ^b,e,g,h   Ayukawa, Kazushige ^b   Soga, Mitsuru ^b   Tanaka, Yuji ^b   Sugie, Yoshimitsu ^b   Nakagome, Yoshinobu ^a,b  

^a IEEE   (Japan)

^b HITACHI LTD   (Japan)

^c UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

^d TOHOKU UNIVERSITY   (Japan)

^e University of Electro Communications ^*

^f WASEDA UNIVERSITY   (Japan)

^g UNIVERSITY OF FUKUI   (Japan)

^h Institute of Electronics   (Japan)

Author keywords

3 D CG; Computer graphics; DRAM; DRAM macro; Embedded DRAM; Media chip

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA TRANSFER; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MACROS; REAL TIME SYSTEMS; THREE DIMENSIONAL COMPUTER GRAPHICS;

DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE; LOGIC MEMORY INTERFACE; MULTIMEDIA CHIP;

RANDOM ACCESS STORAGE;

EID: 0031145559     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.568823     Document Type: Article

References (10)

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