Parallel matrix multiplication on a linear array with a reconfigurable pipelined bus system

IEEE Transactions on Computers

Volumn 50, Issue 5, 2001, Pages 519-525

  Li, Keqin ^a,b   Pan, Victor Y ^c  

^a IEEE   (United States)

^b STATE UNIVERSITY OF NEW YORK   (United States)

^c CITY UNIVERSITY OF NEW YORK   (United States)

Author keywords

Bilinear algorithm; Cost optimality; Distributed memory system; Linear array; Matrix multiplication; Optical pipelined bus; PRAM; Reconfigurable system; Speedup

Indexed keywords

LINEAR ARRAY; MATRIX MULTIPLICATION;

ALGORITHMS; MATRIX ALGEBRA; MULTIPLYING CIRCUITS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE;

PIPELINE PROCESSING SYSTEMS;

EID: 0035335256     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.926164     Document Type: Article

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