Numerical analysis on the LDMOS with a double epi-layer and trench electrodes

Microelectronics Journal

Volumn 32, Issue 5-6, 2001, Pages 497-502

  Park, I Y ^a,d   Choi, Y I ^a   Chung, S K ^a   Lim, H J ^a   Mo, S I ^a   Choi, J S ^b   Han, M K ^c  

^a Ajou University   (South Korea)

^b Division of Semiconductor   (South Korea)

^c Seoul National University   (South Korea)

^d Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Double epi layer; High drift current density; LDMOS; RESURF technique; Trenched electrodes

Indexed keywords

CURRENT DENSITY; ELECTRIC BREAKDOWN; ELECTRIC RESISTANCE; ELECTRODES; GATES (TRANSISTOR); SEMICONDUCTING FILMS; SEMICONDUCTOR DEVICE STRUCTURES; SUBSTRATES;

DOUBLE EPITAXIAL LAYERS; TRENCH ELECTRODES;

MOSFET DEVICES;

EID: 0035333518     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(01)00021-0     Document Type: Article

References (7)

1. 2 n-channel LDMOS in a 0.65 μm smart power technology for 20-30 V applications
2. A new concept for the lateral DMOS transistor for smart power IC's
3. A trench lateral power MOSFET using self-aligned trench bottom contact holes
4. 16-60 V rated LDMOS show advanced performance in an 0.72 μm evolution BiCMOS power technology
5. 20 V LDMOS optimized for high drain current conditions which is better, n-epi or p-epi?
6. An optimized RESURF LDMOS power device module compatible with advanced logic processes
7. New 3-D lateral power MOSFETs with ultra low on-resistance