360MHz 3V CMOS PLL with 1V peak-to-peak power supply noise tolerance

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 134-135

  Zhang, Zhong Xuan ^a   Du, He ^a   Lee, Man Shek ^a  

^a Cirrus Logic   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL FILTERS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY RESPONSE; MOSFET DEVICES; SENSITIVITY ANALYSIS; SIGNAL FILTERING AND PREDICTION; SPURIOUS SIGNAL NOISE; TRANSFER FUNCTIONS; VARIABLE FREQUENCY OSCILLATORS;

HIGH NOISE IMMUNITY; JITTER; NOISE INJECTION; NOISE TOLERANCE; NOISE VOLTAGE; PHASE NOISE;

PHASE LOCKED LOOPS;

EID: 0030086654     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)