Fully-integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 38, Issue , 1995, Pages

  Novof, Ilya ^a   Austin, John ^a   Chmela, Russ ^a   Frank, Todd ^a   Kelkar, Ram ^a   Short, Ken ^a   Strayer, Don ^a   Styduhar, Mark ^a   Wyatt, Steve ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; SIGNAL FILTERING AND PREDICTION; SPURIOUS SIGNAL NOISE; SYNCHRONIZATION;

CLOCK DISTRIBUTION; CLOCK PHASE SYNCHRONIZATION; FREQUENCY SYNTHESIS; JITTER; LOOP STABILIZATION; SUPPLY NOISE;

PHASE LOCKED LOOPS;

EID: 0029255343     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)