Software energy reduction techniques for variable-voltage processors

IEEE Design and Test of Computers

Volumn 18, Issue 2, 2001, Pages 31-41

  Okuma, Takanori ^a   Yasuura, Hiroto ^a,c   Ishihara, Tohru ^b,d  

^a KYUSHU UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c Institute of Systems & Information Technologies/KYUSHU   (Japan)

^d IEEE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CENTRAL PROCESSING UNIT; SYSTEM-ON-CHIP; VARIABLE VOLTAGE PROCESSOR; VOLTAGE SCHEDULING TECHNIQUE;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC GATES; MOSFET DEVICES; REAL TIME SYSTEMS; SCHEDULING;

PROGRAM PROCESSORS;

EID: 0035280198     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.914613     Document Type: Article

References (10)

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2. T. Okuma, T. Ishihara, and H. Yasuura, "Real-Time Task Scheduling for a Variable-Voltage Processor," Proc. 12th Int'l Symp. System Synthesis (ISSS 98), IEEE CS Press, Los Alamitos, Calif., 1999, pp. 25-29.
3. S. Lee and T. Sakurai, "Run-Time Power Control Scheme Using Software Feedback Loop for Low-Power Real-Time Application," Proc. 2000 Asia and South Pacific Design Automation Conf. (ASP-DAC 2000), ACM Press, New York, 2000, pp. 381-386.
4. S. Lee and T. Sakurai, "Run-Time Voltage Hopping for Low-Power Real-Time Systems," Proc. 37th Design Automation Conf. (DAC 00), ACM Press, New York, 2000, pp. 806-809.
5. "Crusoe Processor," Transmeta Corp., Santa Clara, Calif., http://www.transmeta.com/crusoe/.
6. I. Hong et al., "Power Optimization of Variable Voltage Core-Based Systems," Proc. 35th Design Automation Conf. (DAC 98), ACM Press, New York, 1998, pp. 176-181.
7. I. Hong, M. Potkonjak, and M.B. Srivastava, "On-Line Scheduling of Hard Real-Time Tasks on Variable-Voltage Processor," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 98), ACM Press, New York, 1998, pp. 653-656.
8. Y. Shin and K. Choi, "Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems," Proc. 36th Design Automation Conf. (DAC 99), ACM Press, New York, 1999, pp. 134-139.
9. T. Pering, T. Burd, and R. Brodersen, "Voltage Scheduling in the IpARM Microprocessor System," Proc. Int'l Symp. Low Power Electronics and Design (ISPLED 00), ACM Press, New York, 2000, pp. 96-101.
10. T. Burd et al., "A Dynamic Voltage Scaled Microprocessor System," Proc. IEEE Int'l Solid-State Circuits Conf. (2000 ISSCC), IEEE Press, Piscataway, N.J., 2000, pp. 294-295.