|
Volumn 1, Issue , 1984, Pages 221-225
|
ON TESTABILITY ANALYSIS OF COMBINATIONAL NETWORKS.
a |
Author keywords
[No Author keywords available]
|
Indexed keywords
ELECTRONIC CIRCUITS, DIGITAL;
DESIGN FOR TESTABILITY;
FAULT COVERAGE;
LARGE COMBINATIONAL MODULES;
TEST PATTERN EFFECTIVENESS;
TEST PATTERN GENERATION;
TESTABILITY ALGORITHMS;
LOGIC CIRCUITS, COMBINATORIAL;
|
EID: 0021582621
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (100)
|
References (7)
|