Multiple layers of CMOS integrated circuits using recrystallized silicon film

IEEE Electron Device Letters

Volumn 22, Issue 2, 2001, Pages 77-79

  Chan, Victor W C ^a   Chan, Philip C H ^a   Chan, Man Sun ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS SILICON; DIELECTRIC MATERIALS; GRAIN SIZE AND SHAPE; LAYERED MANUFACTURING; SILICON ON INSULATOR TECHNOLOGY;

METAL INDUCED LATERAL CRYSTALLIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 0035249020     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.902837     Document Type: Article

References (7)

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3. S. Pae et al., "Multiple layers of silicon-on-insulator (MLSOI) islands fabrication process and fully-depleted SOI pMOSFETs," in IEEE SOI Conf., Oct. 1999, pp. 15-16.
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6. V. Subramanian and K. Saraswat, "High performance germanium-seeded laterally crystallized TFT's for vertical device integration," IEEE Trans. Electron Devices, vol. 46, pp. 1934-1939, Oct. 1999.
7. H. Wang et al., "Super thin-film transistor with SOI CMOS performance formed hy a novel grain enhancement method," IEEE Trans. Electron Devices, vol. 47, pp. 1580-1586, Aug. 2000.