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Volumn , Issue , 1999, Pages 164-172

Analytical model for high level power modeling of combinational and sequential circuits

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; SEQUENTIAL CIRCUITS; TIMING CIRCUITS;

EID: 22544484821     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPD.1999.750417     Document Type: Conference Paper
Times cited : (40)

References (20)
  • 1
    • 0028711580 scopus 로고
    • A survey of power estimation techniques in VLSI circuits
    • Dec.
    • F. N. Najm, "A survey of power estimation techniques in VLSI circuits, " IEEE Transactions on VLSI Systems, pp. 446-455, Dec. 1994.
    • (1994) IEEE Transactions on VLSI Systems , pp. 446-455
    • Najm, F.N.1
  • 3
    • 0030173035 scopus 로고    scopus 로고
    • Towards a high-level power estimation capability
    • June
    • M. Nemani and F. N. Najm, "Towards a High-Level Power Estimation Capability, " IEEE Transac-tions on CAD, vol. 15 pp. 588-598, June 1996.
    • (1996) IEEE Transac-tions on CAD , vol.15 , pp. 588-598
    • Nemani, M.1    Najm, F.N.2
  • 5
    • 0000433583 scopus 로고
    • Estimating power dissipation of VLSI signal processing chips: The PFA technique
    • S. R. Powell and P. M. Chau, " Estimating Power Dissipation of VLSI signal Processing Chips: The PFA technique, " VLSI Signal Processing IV, pp. 250-259, 1990.
    • (1990) VLSI Signal Processing IV , pp. 250-259
    • Powell, S.R.1    Chau, P.M.2
  • 6
    • 0000440896 scopus 로고
    • Architectural power analysis: The dual bit type method
    • June
    • P. E. Landman and J. M. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method, " IEEE Transactions on VLSI, vol. 3 pp. 173-187 June 1995.
    • (1995) IEEE Transactions on VLSI , vol.3 , pp. 173-187
    • Landman, P.E.1    Rabaey, J.M.2
  • 8
    • 0030383438 scopus 로고    scopus 로고
    • Register-transfer level estimation techniques for switch-ing activity and power consumption
    • November
    • A. Raghunathan, S. Dey and N. K. Jha, "Register-Transfer Level Estimation Techniques for Switch-ing Activity and Power Consumption, " IEEE International Conference on Computer-Aided Design, pp. 158-165, November 1996.
    • (1996) IEEE International Conference on Computer-Aided Design , pp. 158-165
    • Raghunathan, A.1    Dey, S.2    Jha, N.K.3
  • 12
    • 0027544156 scopus 로고
    • Transition density: A new measure of activity in digital circuits
    • Feb.
    • F. N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits, " IEEE Trans. on CAD, vol. 12, pp. 310-323, Feb. 1993.
    • (1993) IEEE Trans. on CAD , vol.12 , pp. 310-323
    • Najm, F.N.1
  • 14
    • 0002609165 scopus 로고
    • A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran
    • June
    • F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran, " IEEE International Symposium on Circuits and Systems, pp. 695-698, June 1985.
    • (1985) IEEE International Symposium on Circuits and Systems , pp. 695-698
    • Brglez, F.1    Fujiwara, H.2
  • 16
    • 0028573885 scopus 로고
    • Statistical estimation of the switching activity in digital circuits
    • June
    • M. Xakellis and F. N. Najm, "Statistical Estimation of the Switching Activity in Digital Circuits, " 31st ACM/IEEE Design Automation Conference, pp. 728-733, June 1994.
    • (1994) 31st ACM/IEEE Design Automation Conference , pp. 728-733
    • Xakellis, M.1    Najm, F.N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.