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Volumn , Issue , 1998, Pages 64-67
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On the impact of dishing in metal CMP processes on circuit performance
a a |
Author keywords
[No Author keywords available]
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Indexed keywords
CHEMICAL POLISHING;
ELECTRIC NETWORK ANALYSIS;
INTEGRATED CIRCUIT LAYOUT;
MATHEMATICAL MODELS;
CHEMICAL MECHANICAL POLISHING (CMP);
DISHING;
VLSI CIRCUITS;
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EID: 0032268774
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Article |
Times cited : (6)
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References (4)
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