-
1
-
-
0016313256
-
A comparison of list scheduling for parallel processing systems
-
Dec.
-
ADAM, T. L., CHANDY, K. M., AND DICKSON, J. R. 1974. A comparison of list scheduling for parallel processing systems. Commun. ACM 17, 12 (Dec.), 685-690.
-
(1974)
Commun. ACM
, vol.17
, Issue.12
, pp. 685-690
-
-
Adam, T.L.1
Chandy, K.M.2
Dickson, J.R.3
-
2
-
-
0004072686
-
-
Addison-Wesley Longman Publ. Co., Inc., Reading, MA
-
AHO, A. V., SETHI, R., AND ULLMAN, J. D. 1986. Compilers: Principles, Techniques, and Tools. Addison-Wesley Longman Publ. Co., Inc., Reading, MA.
-
(1986)
Compilers: Principles, Techniques, and Tools
-
-
Aho, A.V.1
Sethi, R.2
Ullman, J.D.3
-
3
-
-
84976702085
-
Perfect pipelining: A new loop parallelization technique
-
(New York, Mar.), H. Ganzinger, Ed.
-
AIKEN, A. AND NICOLAU, A. 1988. Perfect pipelining: A new loop parallelization technique. In Proceedings of the 2nd European Symposium on Programming (New York, Mar.), H. Ganzinger, Ed. 221-235.
-
(1988)
Proceedings of the 2nd European Symposium on Programming
, pp. 221-235
-
-
Aiken, A.1
Nicolau, A.2
-
4
-
-
0028508203
-
Instruction scheduling in the TOBEY compiler
-
Sept.
-
BLAINEY, R. J. 1994. Instruction scheduling in the TOBEY compiler. IBM J. Res. Dev. 38, 5 (Sept.), 577-593.
-
(1994)
IBM J. Res. Dev.
, vol.38
, Issue.5
, pp. 577-593
-
-
Blainey, R.J.1
-
6
-
-
0019610938
-
An approach to scientific array processing: The architectural design of the AP-120B/FPS family
-
Sept.
-
CHARLESWORTH, A. E. 1981. An approach to scientific array processing: The architectural design of the AP-120B/FPS family. Computer 14, 9 (Sept.), 18-27.
-
(1981)
Computer
, vol.14
, Issue.9
, pp. 18-27
-
-
Charlesworth, A.E.1
-
7
-
-
0029308368
-
Effective hardware-based data prefetching for high-performance processors
-
May
-
CHEN, T. F. AND BEAR, J. L. 1995. Effective hardware-based data prefetching for high-performance processors. IEEE Trans. Comput. 44, 5 (May), 609-623.
-
(1995)
IEEE Trans. Comput.
, vol.44
, Issue.5
, pp. 609-623
-
-
Chen, T.F.1
Bear, J.L.2
-
8
-
-
0019595341
-
Some experiments in local microcode compaction for horizontal machines
-
July
-
DAVIDSON, S., LANDSKOV, D., SHRIVER, B. D., AND MALLET, P. W. 1981. Some experiments in local microcode compaction for horizontal machines. IEEE Trans. Comput. C-30, 7 (July), 460-477.
-
(1981)
IEEE Trans. Comput.
, vol.C-30
, Issue.7
, pp. 460-477
-
-
Davidson, S.1
Landskov, D.2
Shriver, B.D.3
Mallet, P.W.4
-
9
-
-
0029200684
-
Performance evaluation of the PowerPC 620 micro-architecture
-
Santa Margherita Ligure, Italy, June 22-24. ACM Press, New York, NY
-
DIEP, T. A., NELSON, C., AND SHEN, J. P. 1995. Performance evaluation of the PowerPC 620 micro-architecture. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95, Santa Margherita Ligure, Italy, June 22-24). ACM Press, New York, NY, 163-174.
-
(1995)
Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95)
, pp. 163-174
-
-
Diep, T.A.1
Nelson, C.2
Shen, J.P.3
-
10
-
-
0023209052
-
Branch folding in the CRISP microprocessor: Reducing branch delay to zero
-
Pittsburgh, PA, June 2-5, D. St. Clair, Ed. ACM Press, New York, NY
-
DITZEL, D. R. AND MCLELLAN, H. R. 1987. Branch folding in the CRISP microprocessor: Reducing branch delay to zero. In Proceedings of the 14th Annual International Symposium on Computer Architecture (ISCA '87, Pittsburgh, PA, June 2-5), D. St. Clair, Ed. ACM Press, New York, NY, 2-8.
-
(1987)
Proceedings of the 14th Annual International Symposium on Computer Architecture (ISCA '87)
, pp. 2-8
-
-
Ditzel, D.R.1
Mclellan, H.R.2
-
11
-
-
0029292848
-
Superscalar instruction execution in the 21164 Alpha microprocessor
-
Apr.
-
EDMONDSON, J. H., RUBINFELD, P., PRESTON, R., AND RAJAGOPALAN, V. 1995. Superscalar instruction execution in the 21164 Alpha microprocessor. IEEE Micro 15, 2 (Apr.), 33-43.
-
(1995)
IEEE Micro
, vol.15
, Issue.2
, pp. 33-43
-
-
Edmondson, J.H.1
Rubinfeld, P.2
Preston, R.3
Rajagopalan, V.4
-
13
-
-
0345994345
-
-
Ph.D. dissertation, Tech. Rep. COO-3077-161. Courant Mathematics and Computing Laboratory, New York University, New York, NY
-
FISHER, J. A. 1979. The optimum of horizontal microcode within and beyond basic blocks: An application of processor scheduling with resources. Ph.D. dissertation, Tech. Rep. COO-3077-161. Courant Mathematics and Computing Laboratory, New York University, New York, NY.
-
(1979)
The Optimum of Horizontal Microcode Within and Beyond Basic Blocks: An Application of Processor Scheduling with Resources.
-
-
Fisher, J.A.1
-
14
-
-
0026918392
-
Predicting conditional branch directions from previous runs of a program
-
Boston, MA, Oct. 12-15. ACM Press, New York, NY
-
FISHER, J. A. AND FREUDENBERGER, S. M. 1992. Predicting conditional branch directions from previous runs of a program. In Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-V, Boston, MA, Oct. 12-15). ACM Press, New York, NY, 85-95.
-
(1992)
Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-V)
, pp. 85-95
-
-
Fisher, J.A.1
Freudenberger, S.M.2
-
15
-
-
0026962180
-
Stride directed prefetching in scalar processors
-
MICRO 25, Portland, OR, Dec. 1-4. IEEE Computer Society Press, Los Alamitos, CA
-
FUAND, J. W. C. AND PATEL, J. H. 1992. Stride directed prefetching in scalar processors. In Proceedings of the 25th Annual International Symposium on Microarchitecture (MICRO 25, Portland, OR, Dec. 1-4). IEEE Computer Society Press, Los Alamitos, CA, 102-110.
-
(1992)
Proceedings of the 25th Annual International Symposium on Microarchitecture
, pp. 102-110
-
-
Fuand, J.W.C.1
Patel, J.H.2
-
16
-
-
0004100570
-
Speculative execution based on value prediction
-
Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa, Israel
-
GABBAY, F. AND MENDELSON, A. 1996. Speculative execution based on value prediction. Tech. Rep. 1080. Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa, Israel.
-
(1996)
Tech. Rep. 1080
-
-
Gabbay, F.1
Mendelson, A.2
-
20
-
-
0002284699
-
Intel's P6 uses decoupled superscalar design
-
Feb.
-
GWENNAP, L. 1995. Intel's P6 uses decoupled superscalar design. Microprocess. Rep. 9, 2 (Feb.).
-
(1995)
Microprocess. Rep.
, vol.9
, Issue.2
-
-
Gwennap, L.1
-
21
-
-
0016644685
-
Look-ahead processors
-
Dec.
-
KELLER, R. M. 1975. Look-ahead processors. ACM Comput. Surv. 7, 4 (Dec.), 177-195.
-
(1975)
ACM Comput. Surv.
, vol.7
, Issue.4
, pp. 177-195
-
-
Keller, R.M.1
-
23
-
-
0042650298
-
Software pipelining: An effective scheduling technique for VLIW machines
-
Atlanta, GA, June 22-24, R. L. Wexelblat, Ed. ACM Press, New York, NY
-
LAM, M. S. 1988. Software pipelining: An effective scheduling technique for VLIW machines. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '88, Atlanta, GA, June 22-24), R. L. Wexelblat, Ed. ACM Press, New York, NY, 318-328.
-
(1988)
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '88)
, pp. 318-328
-
-
Lam, M.S.1
-
25
-
-
17044425961
-
Value locality and load value prediction
-
ACM Press, New York, NY
-
LIPASTI, M. H., WILKERSON, C. B., AND SHEN, J. P. 1996a. Value locality and load value prediction. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII). ACM Press, New York, NY.
-
(1996)
Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII)
-
-
Lipasti, M.H.1
Wilkerson, C.B.2
Shen, J.P.3
-
26
-
-
0030395192
-
Exceeding the dataflow limit via value prediction
-
ACM, New York, NY
-
LIPASTI, M. H., WILKERSON, C. B., AND SHEN, J. P. 1996b. Exceeding the dataflow limit via value prediction. In Proceedings of the 29th Annual ACMI IEEE International Symposium on Microarchitecture. ACM, New York, NY.
-
(1996)
Proceedings of the 29th Annual ACMI IEEE International Symposium on Microarchitecture
-
-
Lipasti, M.H.1
Wilkerson, C.B.2
Shen, J.P.3
-
27
-
-
0022583632
-
Reducing the cost of branches
-
Tokyo, Japan, June 2-5. IEEE Computer Society Press, Los Alamitos, CA
-
MCFARLING, S. AND HENNESSY, J. 1986. Reducing the cost of branches. In Proceedings of the 13th Annual International Symposium on Computer Architecture (ISCA '86, Tokyo, Japan, June 2-5). IEEE Computer Society Press, Los Alamitos, CA, 396-403.
-
(1986)
Proceedings of the 13th Annual International Symposium on Computer Architecture (ISCA '86)
, pp. 396-403
-
-
Mcfarling, S.1
Hennessy, J.2
-
29
-
-
0003015894
-
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing
-
RAU, B. R. AND GLAESER, C. D. 1981. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In Proceedings of the 14th Annual Workshop on Microprogramming. 183-198.
-
(1981)
Proceedings of the 14th Annual Workshop on Microprogramming
, pp. 183-198
-
-
Rau, B.R.1
Glaeser, C.D.2
-
30
-
-
0029178659
-
Implementation trade-offs in using restricted data flow architecture in high performance RISC microprocessors
-
Santa Margherita Ligure, Italy, June 22-24. ACM Press, New York, NY
-
SIMONE, M., ESSEN, A., IKE, A., KRISHNAMOORTHY, A., MARUYAMA, T., PATKAR, N., RAMASWAMI, M., SHEBANOW, M., THIRUMALAISWAMY, V., AND TOVEY, D. 1995. Implementation trade-offs in using restricted data flow architecture in high performance RISC microprocessors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95, Santa Margherita Ligure, Italy, June 22-24). ACM Press, New York, NY, 151-162.
-
(1995)
Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95)
, pp. 151-162
-
-
Simone, M.1
Essen, A.2
Ike, A.3
Krishnamoorthy, A.4
Maruyama, T.5
Patkar, N.6
Ramaswami, M.7
Shebanow, M.8
Thirumalaiswamy, V.9
Tovey, D.10
-
31
-
-
0347739634
-
Introduction to Shade
-
Revision A of 1/Apr/92. Sun Microsystems, Inc., Mountain View, CA
-
SUN MICROSYSTEMS. 1992. Introduction to Shade. Tech. Rep. 415-960-1300 (Revision A of 1/Apr/92). Sun Microsystems, Inc., Mountain View, CA.
-
(1992)
Tech. Rep. 415-960-1300
-
-
-
32
-
-
0021204160
-
Branch prediction strategies and branch-target buffer design
-
Jan.
-
SMITH, A. AND LEE, J. 1984. Branch prediction strategies and branch-target buffer design. Computer 17, 1 (Jan.), 6-22.
-
(1984)
Computer
, vol.17
, Issue.1
, pp. 6-22
-
-
Smith, A.1
Lee, J.2
-
34
-
-
0003081830
-
An efficient algorithm for exploiting multiple arithmetic units
-
Jan.
-
TOMASULO, R. M. 1967. An efficient algorithm for exploiting multiple arithmetic units. IBM J. Res. Dev. 11, 1 (Jan.), 25-33.
-
(1967)
IBM J. Res. Dev.
, vol.11
, Issue.1
, pp. 25-33
-
-
Tomasulo, R.M.1
-
35
-
-
0026137115
-
Limits of instruction-level parallelism
-
Santa Clara, CA, Apr. 8-11. ACM Press, New York, NY
-
WALL, D. W. 1991. Limits of instruction-level parallelism. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV, Santa Clara, CA, Apr. 8-11). ACM Press, New York, NY, 248-259.
-
(1991)
Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV)
, pp. 248-259
-
-
Wall, D.W.1
-
36
-
-
0023601205
-
A study of scalar compilation techniques for pipelined supercomputers
-
Palo Alto, CA, Oct. 5-8, R. Katz, Ed. IEEE Computer Society Press, Los Alamitos, CA
-
WEISS, S. AND SMITH, J. E. 1987. A study of scalar compilation techniques for pipelined supercomputers. In Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems (APLOS II, Palo Alto, CA, Oct. 5-8), R. Katz, Ed. IEEE Computer Society Press, Los Alamitos, CA, 105-109.
-
(1987)
Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems (APLOS II)
, pp. 105-109
-
-
Weiss, S.1
Smith, J.E.2
-
37
-
-
85034094146
-
Two-level adaptive training branch prediction
-
MICRO 24, Albuquerque, NM, Nov. 18-20. ACM Press, New York, NY
-
YEH, T.-Y. AND PATT, Y. N. 1991. Two-level adaptive training branch prediction. In Proceedings of the 24th Annual International Symposium on Microarchitecture (MICRO 24, Albuquerque, NM, Nov. 18-20). ACM Press, New York, NY, 51-61.
-
(1991)
Proceedings of the 24th Annual International Symposium on Microarchitecture
, pp. 51-61
-
-
Yeh, T.-Y.1
Patt, Y.N.2
-
38
-
-
0026867221
-
Alternative implementation of two-level adaptive branch prediction
-
Gold Coast, Australia, May 19-21. ACM Press, New York, NY
-
YEH, T. Y. AND PATT, Y. N. 1992. Alternative implementation of two-level adaptive branch prediction. In Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA '92, Gold Coast, Australia, May 19-21). ACM Press, New York, NY, 124-134.
-
(1992)
Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA '92)
, pp. 124-134
-
-
Yeh, T.Y.1
Patt, Y.N.2
-
39
-
-
0027307813
-
A comparison of dynamic branch predictors that uses two levels of branch history
-
San Diego, CA, May 16-19. ACM Press, New York, NY
-
YEH, T. Y. AND PATT, Y. N. 1993. A comparison of dynamic branch predictors that uses two levels of branch history. In Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA '94, San Diego, CA, May 16-19). ACM Press, New York, NY, 257-266.
-
(1993)
Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA '94)
, pp. 257-266
-
-
Yeh, T.Y.1
Patt, Y.N.2
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