Load redundancy removal through instruction reuse

Proceedings of the International Conference on Parallel Processing

Volumn 2000-January, Issue , 2000, Pages 61-68

  Yang, Jun ^a   Gupta, R ^a  

^a University of Arizona   (United States)

Author keywords

Computer aided instruction; Computer science; Degradation; Delay; Hardware; History; Microarchitecture; Redundancy; Runtime

Indexed keywords

COMPUTER HARDWARE; COMPUTER SCIENCE; DEGRADATION; HARDWARE; HISTORY; REDUNDANCY;

CACHE MISS; DELAY; EXECUTION HISTORY; HARDWARE IMPLEMENTATIONS; INSTRUCTION REUSE; MICRO ARCHITECTURES; REDUNDANCY REMOVAL; RUNTIMES;

COMPUTER AIDED INSTRUCTION;

EID: 0003576798     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2000.876075     Document Type: Conference Paper

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