MAGELLAN: Multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs

Hardware/Software Codesign - Proceedings of the International Workshop

Volumn , Issue , 2001, Pages 42-47

  Chatha, K S ^a   Vemuri, R ^a  

^a University of Cincinnati   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER GRAPHICS; DATA FLOW ANALYSIS; HEURISTIC METHODS; IMAGE COMPRESSION; ITERATIVE METHODS; MAPPING;

HIERARCHICAL CONTROL-DATAFLOW TASK GRAPHS;

EMBEDDED SYSTEMS;

EID: 0034821695     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

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6. Loop pipelining in hardware-software partitioning
7. RECOD: A retiming heuristic to optimize resource and memory utilization in HW/SW codesigns
8. COSYN: Hardware-software cosynthesis for heterogeneous distributed embedded systems
9. An iterative algorithm for hardware-software partitioning, hardware design space exploration and scheduling