D30V/MPEG multimedia processor

IEEE Micro

Volumn 19, Issue 4, 1999, Pages 38-47

  Takata, Hidehiro ^a   Watanabe, Tetsuya ^b   Nakajima, Tetsuo ^b   Takagaki, Takashi ^b   Sato, Hisakazu ^b   Mohri, Atsushi ^b   Yamada, Akira ^b   Kanamoto, Toshiki ^b   Matsuda, Yoshio ^b   Iwade, Shuhei ^b   Horiba, Yasutaka ^b  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DECODING; IMAGE CODING; IMAGE COMPRESSION; INTEGRATED CIRCUIT LAYOUT; MULTIMEDIA SYSTEMS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; STANDARDS;

CYCLIC REDUNDANCY CHECK; D30V MPEG MULTIMEDIA PROCESSOR; MOTION PICTURES EXPERT GROUP;

MICROPROCESSOR CHIPS;

EID: 0032592097     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.782566     Document Type: Article

References (7)

1. M. Mizuno et al., "A 1.5W Single-Chip MPEG-2 MP@ML Encoder with Low-Power Motion Estimation and Clocking," ISSCC Digest of Technical Papers, IEEE Press, Piscataway, N.J., 1997, pp. 256-257.
2. T. Yoshida et al., "A 2V 250MHz Multimedia Processor," ISSCC Digest of Technical Papers, 1997, pp. 266-267.
3. A. Yamada et al., "Real-Time MPEG-2 Encoding and Decoding with a Dual-Issue RISC Processor," Proc. IEEE Custom Integrated Circuits Conf., IEEE Press, 1997, pp. 225-228.
4. H. Takata et al., "2V 250MHz Multimedia Processor Design," Proc. Int'l Workshop Advanced LSIs, IEEE Electron Devices Society, Tokyo Chapter, 1997, pp. 124-131.
5. ISO-IEC/JTC1 SC29, DIS 13818, Part 2, Int'l Organization for Standardization, Geneva, 1994.
6. A. Mohri et al., "A Real-Time Digital VCR Encode/Decode and MPEG-2 Decode LSI Implemented on Dual-Issue RISC Processor," Proc. 24th European Solid-State Circuits Conf., IEEE Press, 1998. pp. 180-183.
7. E. Holmann et al., "Real-Time MPEG-2 Software Decoding with a Dual-Issue RISC Processor," Proc. VLSI Signal Processing IX, 1996, pp. 105-114.