Challenge of a multiple-valued technology in recent deep-submicron VLSI

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2001, Pages 241-244

  Hanyu, T ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MOS DEVICES;

DEEP-SUBMICRON TECHNOLOGY;

VLSI CIRCUITS;

EID: 0034821202     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

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