Parametric yield enhancement system via circuit level device optimization using statistical circuit simulation

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 163-166

  Miyama, M ^a   Kamohara, S ^a   Okuyama, K ^a   Oji, Y ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MONTE CARLO METHODS; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

PARAMETRIC YIELD ENHANCEMENT SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 0034794608     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. E-T based statistical modeling and compact statistical circuit simulation methodologies
2. An efficient statistical model using electrical tests for GHz CMOS devices
3. The impact of device scaling and power supply change on CMOS gate performance
4. Gate oxide scaling limits and projection
5. Realistic worst-case spice file extraction using BSIM3
6. Circuit sensitivity to interconnect variation
7. Statistical BSIM3 model parameter extraction and fast/slow model parameter determination for high speed SRAM parametric yield estimation