Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2001, Pages 221-226

  Park, J ^a   Diniz, P C ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

FPGA based configurable computing; Hardware Interfaces and Customizable Memory Controllers; Scheduling of Memory Accesses

Indexed keywords

BANDWIDTH; IMAGE PROCESSING; PIPELINE PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; SCHEDULING;

PIPELINED MEMORY ACCESS CONTROLLERS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034790529     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/500001.500054     Document Type: Conference Paper

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