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Volumn 2, Issue , 2000, Pages

G-link and gigabit ethernet compliant serializer for LHC data transmission

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COLLIDING BEAM ACCELERATORS; COMPUTER NETWORKS; DATA ACQUISITION; DATA COMMUNICATION SYSTEMS; DOSIMETRY; IRRADIATION; OPTICAL LINKS;

EID: 0034593851     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (39)

References (12)
  • 4
    • 0013446346 scopus 로고    scopus 로고
    • The 12C-BUS specification
    • Philips Semiconductors,Version 2.1, January
    • "The 12C-BUS specification", Philips Semiconductors,Version 2.1, January 2000
    • (2000)
  • 5
    • 0003858620 scopus 로고
    • The test access port and boundary-scan architecture
    • IEEE Computer Society Press
    • C. M. Maunder and R. E. Tulloss, "The Test Access Port and Boundary-Scan Architecture," IEEE Computer Society Press, 1990
    • (1990)
    • Maunder, C.M.1    Tulloss, R.E.2
  • 6
    • 0002354984 scopus 로고    scopus 로고
    • Development of a radiation tolerant 2.0V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments
    • Rome
    • K. Kloukinas, F. Faccio, A. Marchioro and P. Moreira, "Development of a radiation tolerant 2.0V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments" Proc. of the fourth workshop on electronics for LHC experiments, pp. 574-580, Rome, 1998
    • (1998) Proc. of the Fourth Workshop on Electronics for LHC Experiments , pp. 574-580
    • Kloukinas, K.1    Faccio, F.2    Marchioro, A.3    Moreira, P.4
  • 7
    • 0030290680 scopus 로고    scopus 로고
    • Low-jitter process-independent DLL and PLL based on self-biased techniques
    • Nov.
    • J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 30, pp. 1259-1266, Nov. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 1723-1732
    • Maneatis, J.1
  • 8
    • 0029408024 scopus 로고    scopus 로고
    • Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter
    • Nov.
    • I. Novof, J. Austin, R. Kelkar, D. Strayer and S. Wyatt, "Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ±50 ps jitter," IEEE J. Solid-State Circuits, vol. 30, pp. 1259-1266, Nov. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.30 , pp. 1259-1266
    • Novof, I.1    Austin, J.2    Kelkar, R.3    Strayer, D.4    Wyatt, S.5
  • 9
    • 20244387403 scopus 로고    scopus 로고
    • Deep submicron CMOS technologies for the LHC experiments
    • P. Jarron, et al., "Deep submicron CMOS technologies for the LHC experiments," Nuclear Physics B (Proc Suppl.), vol. 78, pp. 625-634, 1999
    • (1999) Nuclear Physics B (Proc Suppl.) , vol.78 , pp. 625-634
    • Jarron, P.1
  • 11
    • 0034246091 scopus 로고    scopus 로고
    • Computational method to estimate single event upset rates in an accelerator environment
    • M. Huhtinen and F. Faccio, "Computational method to estimate Single Event Upset rates in an accelerator environment", Nuclear Instruments and Methods A, 450, pp. 155-170, 2000
    • (2000) Nuclear Instruments and Methods A , vol.450 , pp. 155-170
    • Huhtinen, M.1    Faccio, F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.