Deep submicron CMOS technologies for the LHC experiments

Nuclear Physics B - Proceedings Supplements

Volumn 78, Issue 1-3, 1999, Pages 625-634

  Jarron, P ^a   Anelli, G ^a   Calin, T ^d   Cosculluela, J ^d   Campbell, M ^a   Delmastro, M ^a,c   Faccio, F ^a   Giraldo, A ^b   Heijne, E ^a   Kloukinas, K ^a   Letheren, M ^a   Nicolaidis, M ^d   Moreira, P ^a   Paccagnella, A ^b   Marchioro, A ^a   Snoeys, W ^a   Velazco, R ^d  

^a CERN   (Switzerland)

^b UNIVERSITY OF PADOVA   (Italy)

^c Assoc per lo Sviluppo Scientifico   (Italy)

^d TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 20244387403     PISSN: 09205632     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0920-5632(99)00615-5     Document Type: Article

References (22)

1. RD9 final status report, A demonstrator analog signal processing circuit in a radiation hard SOI-CMOS technology, CERN/LHCC 97-1, (1997).
2. RD20 Status report, Development of high resolution silicon strip detectors for experiments at high luminosity at LHC, CERN/LHCC 96-2, (1996).
3. RD29 status report, DMILL, a mixed analog-digital radiation hard technology for high energy physics electronics, CERN/LHCC 97-15 (1997).
4. N. Saks et al., Radiation effects in MOS capacitors with very thin oxides at 80K, IEEE Trans. Nucl. Science, Vol.31, p.1249, 1984
5. N. Saks et al., Generation of interface states by ionizing radiation in very thin MOS oxides, IEEE-Transactions-on-Nuclear-Science, vol. 33, no.6, p.1185-90, Dec. 1986.
6. G. Anelli et al., Total dose behaviour of submicron and deep submicron CMOS technologies, Proceedings of the Third Workshop on Electronics for LHC Experiments, London, Sept. 97, page 139.
7. F. Faccio et al., Estimate of the single event upset (SEU) rate in CMS, Proceedings of the Fourth Workshop on Electronics for LHC Experiments, Rome, Sept. 98, p. 119.
8. A. Marchioro, Deep submicron technology for HEP, Proceedings of the Fourth Workshop on Electronics for LHC Experiments, Rome, Sept. 98, p.40.
9. K. Kloukinas et al., Development of a radiation tolerant 2.0V standard cell library using a commercial deep submicron CMOS technology for the LHC experiments, Proceedings of the Fourth Workshop on Electronics for LHC Experiments, Rome, Sept. 98, p.574.
10. P. Jarron, Radiation tolerant electronics for the LHC experiments, Proceedings of the Fourth Workshop on Electronics for LHC Experiments, Rome, Sept 98, p.7
11. W. Snoeys et al., Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel readout chip. Presented at the 8th European Symposium on Semiconductor Detectors, Schloss Elmau, Germany, June 14-17. Submitted to Nuclear Instruments and Methods.
12. M. Campbell et al., A pixel readout chip for 10-30 MRad in standard 0.25mm CMOS, presented at the IEEE Nuclear Science Symposium, 10-14 Nov. 1998, submitted to IEEE Trans. Nucl. Sci.
13. P.V. Dressendorfer, Ionising Radiation Effects in MOS Devices and Circuits, Wiley New York, 1989
14. T.R. Oldham et al., Spatial dependence of holes determined from tunnelling analysis and measured annealing , IEEE Trans. Nucl. Science, Vol.33, No.6, p.1203, December 1986.
15. J.M. Benedetto et al., Hole removal in thin-gate MOSFETS by tunnelling, IEEE Trans. Nucl. Science, Vol.32, No.6, p.3916, December 1985.
16. A. Giraldo, PhD thesis, Padova University, December 1998.
17. R. Velazco et al., 2 CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits, IEEE Trans. Nucl. Science, Vol.41, No.6, p.2229, December 1994.
18. T. Calin et al., Upset hardened memory design for submicron CMOS technology, IEEE Trans. Nucl. Science, Vol.43, No.6, p.2874, December 1996.
19. J. Yuan, C. Svensson, New single-clock CMOS latches and flip-flops with improved speed and power savings, IEEE Journal of Solid-state Circuits, Vol.32, No.1, Jan. 1997
20. T. Aoki, Dynamics of heavy-ion-induced latchup in CMOS structure", IEEE Trans. El. Dev, Vol.35, No.11, p.1885, November 1988.
21. F.Faccio, C.Detcheverry, M.Huhtinen, First Evaluation of the Single Event Upset (SEU) Risk for Electronics in the CMS Experiment, CERN CMS NOTE 1998/054 (1998).
22. G.C. Messenger, M.S. Ash, Single Event Phenomena, Chapman & Hall, 1997.