Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50 ps Jitter

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 11, 1995, Pages 1259-1266

  Strayer, Don ^b   Austin, John ^a   Kelkar, Ram ^a   Wyatt, Steve ^a  

^a IBM MICROELECTRONICS   (United States)

^b Curtiss Wright Controls Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; FREQUENCY SYNTHESIZERS; OSCILLATORS (ELECTRONIC); PULSE GENERATORS; SYNCHRONIZATION;

CURRENT CONTROLLED OSCILLATOR; CURRENT PULSES; FEEDBACK DIVIDER RATIOS; FEEDFORWARD CURRENT INJECTION; FORWARD DIVIDER RATIOS; PULSE MASKING TECHNIQUE; STATIC PHASE ERROR;

PHASE LOCKED LOOPS;

EID: 0029408024     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.475714     Document Type: Article

References (5)

1. Young et al., “PLL clock generator with 5–110 MHz of lock range,” IEEE J. Solid-State Circuits, vol. 27, pp. 1599–1607, Nov. 1992.
2. M. Franz et al., “A 240 MHz phase-locked loop circuit implemented as a standard macro on CMOS SOG gate arrays,” in Proc. IEEE 1992 Custom. Integrated Circuits Conf., May 1992, pp. 25. 1.1–25.1.4.
3. I. Novof et al., “Fully-integrated CMOS phase-locked loop with 15–240 MHz locking range and ±50 ps jitter,” in IEEE 1995 Int. Solid-State Circuit Conf., pp. 112–113.
4. D. Mijuskovic et al., “Cell-based fully integrated CMOS frequency synthesizers,” IEEE J. Solid-State Circuits, vol. 29, pp. 271–280, Mar. 1994.
5. J. Alvarez et al., “A wide-bandwidth low-voltage PLL for power PC microprocessors,” IEEE J. Solid-State Circuits, vol. 30, pp. 383–392, Apr. 1995.