Critical area based yield modeling on an advanced microprocessor design

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue 1, 2000, Pages 191-194

  Segal, Julie ^a   Parker, Susan ^a   Bakarian, Sergei ^a   Pak, James ^a  

^a HPL Technologies Inc   (United States)

Author keywords

Critical area analysis; Defectrelated yield loss; Microprocessor

Indexed keywords

ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; MONTE CARLO METHODS; POLYSILICON; STATISTICS;

CRITICAL AREA ANALYSIS;

MICROPROCESSOR CHIPS;

EID: 0034583846     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Layer yield estimation based on critical area and electrical defect monitor data
2. Application of defect inspection in development of 0.25 and 0.18 micron technology
3. Integrated circuit yield management and yield analysis: Development and implementation
4. Reducing baseline defect density through modeling random defect-limited yield
5. A comparison of efficient dot throwing and shape shifting extra material critical area estimation
6. Impact of simulation parameters on critical area analysis