Layer yield estimation based on critical area and electrical defect monitor data

1999 IEEE International Symposium on Semiconductor Manufacturing, ISSM 1999 - Conference Proceedings

Volumn , Issue , 1999, Pages 99-102

  Milor, L ^a   Hill, G ^a   Peng, Yeng ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; FORECASTING; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; CRYSTAL DEFECTS; INDUSTRIAL ELECTRONICS; PRODUCT DEVELOPMENT; PRODUCTION CONTROL;

ELECTRICAL DEFECTS; LAYOUT DENSITIES; LOCAL INTERCONNECT; PRODUCT YIELDS; RANDOM YIELD LOSS; SINGLE LAYER; YIELD ESTIMATION; YIELD FORECASTING;

PRODUCT DESIGN; SEMICONDUCTOR DEVICE MANUFACTURE;

ELECTRICAL DEFECT MONITORS (DM); YIELD FORECASTING;

EID: 0033329739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSM.1999.808747     Document Type: Conference Paper

References (3)

1. W. Maly and J . Dcszczka, "Yield cstimatitiii nitidel Cor VLSl artwork evaluations, " Election. L ctt. . vol 19. no. 6, pp. 226-227. March 1983.
2. W. Shiudo, R. K. Nurani, and A. J. Stroiwas. "hlTccis of defect propagation. /growth on in-line defect-based yield prediction, " IEEE Trans. Semiconductor Manufacturing, vol. 11, no. 4, pp. 546-551, Nov. 1998.
3. H. T. Heineken and W. Maly, "Manufacturability analysis environment-MAPEX, " Pioc. C1CC, 1994, pp. 309-312.