Synthesis of high-speed pass-transistor logic

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 11, 1997, Pages 974-976

  Oklobdzija, Vojin G ^a   Duchêne, Benoît ^a  

^a University of California Davis   (United States)

Author keywords

CMOS; Pass transistor logic

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; LOGIC DESIGN; LOGIC GATES; TRANSISTORS;

DOUBLE PASS TRANSISTOR LOGIC (DPL);

CMOS INTEGRATED CIRCUITS;

EID: 0031269122     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.644054     Document Type: Article

References (4)

1. K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3.8 ns CMOS 16 16 b multiplier using complementary pass-transistor logic," IEEE]. Solid State Circuits, vol. 25, pp. 388-395, Apr. 1990.
2. M. Suzuki, N. Ohkubo, T. Yamanaka, A. Shimizu, and K. Sasaki, "A 1.5 ns 32 b CMOS ALU in double pass-transistor logic," in 1993ISSCC Dig. Tech. Papers, Feb. 1993, pp. 90-91.
3. K. Yano, K. Sasaki, K. Rikino, and K. Seki, "Lean integration: Achieving a quantum leap in performance and cost of logic LSI's," in Proc. IEEE 1994 Custom Integrated Circuit Conf., San Diego, CA, May 1-4, 1994, pp. 603-606.
4. N. Ohkubo, M. Suzuki, T. Shinbo, and T. Yamanaka, "A 4.4 nS CMOS 54 X 54-b multiplier using pass-transistor multiplexer," in Proc. IEEE 1994 Custom Integrated Circuit Conf., San Diego, CA, May \-$, 1994, pp. 599-602.