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Volumn , Issue , 2000, Pages 254-259

Embedded core testing using genetic algorithms

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED CORE TESTING;

EID: 0034497214     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (13)
  • 1
    • 0030402724 scopus 로고    scopus 로고
    • A unifying methodology for intellectual property and custom logic testing
    • S. Bhatia, T. Gheewala and P. Varma."A unifying methodology for intellectual property and custom logic testing. " Proc. Intl. Test Conf. pp. 639-648, 1996.
    • (1996) Proc. Intl. Test Conf , pp. 639-648
    • Bhatia, S.1    Gheewala, T.2    Varma., P.3
  • 2
    • 0030672498 scopus 로고    scopus 로고
    • Test methodology for embedded cores which protects intellectual property
    • K. De, "Test methodology for embedded cores which protects intellectual property," Proc. VLSI Test Symp. pp. 2-9, 1997.
    • (1997) Proc. VLSI Test Symp , pp. 2-9
    • De, K.1
  • 3
    • 0025480958 scopus 로고
    • Direct access test scheme-design of block and core cells for embedded asics
    • V. Immaneni and S. Raman, "Direct Access Test Scheme-Design of Block and Core Cells for Embedded ASICS. " Proc. Intl. Test Conf. pp. 448-492, 1990.
    • (1990) Proc. Intl. Test Conf , pp. 448-492
    • Immaneni, V.1    Raman, S.2
  • 4
    • 0031361719 scopus 로고    scopus 로고
    • Modifying user-defined logic for test access to embedded cores
    • B. Pouya and N. A. Touba, "Modifying user-defined logic for test access to embedded cores," Proc. Intl. Test Conf. pp. 60-68, 1997.
    • (1997) Proc. Intl. Test Conf , pp. 60-68
    • Pouya, B.1    Touba, N.A.2
  • 5
    • 0030685592 scopus 로고    scopus 로고
    • Testing core-based designs using partial isolation ring
    • N. A. Touba and B. Pouya, "Testing core-based designs using partial isolation ring," Proc. VLSI Test Symp. pp. 10-16, 1997.
    • (1997) Proc. VLSI Test Symp , pp. 10-16
    • Touba, N.A.1    Pouya, B.2
  • 6
    • 0032667182 scopus 로고    scopus 로고
    • Testing embedded-core-based system chips
    • June
    • Y. Zorian, E. J. Marinissen, and S. Dey, "Testing embedded-core-based system chips," IEEE Computer, June 1999, pp. 52-60.
    • (1999) IEEE Computer , pp. 52-60
    • Zorian, Y.1    Marinissen, E.J.2    Dey, S.3
  • 7
    • 0031354471 scopus 로고    scopus 로고
    • A low overhead design for testability and test generation technique for core-based systems
    • I. Ghosh, N. K. Jha, S. Dey, "A low overhead design for testability and test generation technique for core-based systems," Proc. Intl. Test Conf, pp. 50-59, 1997.
    • (1997) Proc. Intl. Test Conf , pp. 50-59
    • Ghosh, I.1    Jha, N.K.2    Dey, S.3
  • 8
    • 0031367231 scopus 로고    scopus 로고
    • Test requirements for embedded core-based systems and
    • Y. Zorian, "Test requirements for embedded core-based systems and IEEE P1500," Proc. Intl. Test Conf, pp. 191-199, 1997.
    • (1997) IEEE P1500 Proc. Intl. Test Conf , pp. 191-199
    • Zorian, Y.1
  • 10
    • 84895184696 scopus 로고    scopus 로고
    • Evaluation for controllability and observability of embedded cores in SOC
    • R. Xu and M. Hsiao, "Evaluation for controllability and observability of embedded cores in SOC," Intl. Test Synthesis Wkshop, 2000.
    • (2000) Intl. Test Synthesis Wkshop
    • Xu, R.1    Hsiao, M.2
  • 11
    • 0029506357 scopus 로고
    • A new architectural-level fault simulation using propagation prediction of grouped fault-effects
    • M. S. Hsiao and J. H. Patel, "A new architectural-level fault simulation using propagation prediction of grouped fault-effects," Proc. Intl. Conf. Computer Design, pp. 628-635, 1995.
    • (1995) Proc. Intl. Conf. Computer Design , pp. 628-635
    • Hsiao, M.S.1    Patel, J.H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.