SCOPUS 정보 검색 플랫폼

IEEE Transactions on Nuclear Science

Volumn 45, Issue 3 PART 3, 1998, Pages 1458-1463

Total dose hardness of three commercial cmos microelectronics foundries

(1) Osborn, J V a

a AEROSPACE CORPORATION (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FOUNDRIES; GATES (TRANSISTOR); MICROELECTRONIC PROCESSING; MOSFET DEVICES; OSCILLATORS (ELECTRONIC); OXIDES; RADIATION EFFECTS; RADIATION HARDENING;

FIELD OXIDE TRANSISTOR; GATE OXIDE; RING OSCILLATORS; THRESHOLD VOLTAGE; TOTAL IONIZING DOSE;

DOSIMETRY;

EID: 0032095217 PISSN: 00189499 EISSN: None Source Type: Journal
DOI: 10.1109/23.685223 Document Type: Article

Times cited : (34)

References (9)

1
- 33747281146
- GOMAC Digest of Papers, March 1996, pp. 175-178.
- J. M. Terrell, S. P. Wong, C. P. Zuhoski, and D. H. Butler Jr. An evaluation of the Radiation Hardended/Tolerant Microelectronics Market", 1996 GOMAC Digest of Papers, March 1996, pp. 175-178.
- An Evaluation of the Radiation Hardended/Tolerant Microelectronics Market", 1996
- Terrell, J.M.¹ Wong, S.P.² Zuhoski, C.P.³ Butler Jr., D.H.⁴

2
- 33747237433
- GOMAC Digest of Papers, March 1996, pp. 411-414.
- B. Bartholet, S. Davis, D. Russell, and M. White Foundry-Flexible ASIC Design for High-Performance Defence, Space, and Commercial Applications", 1996 GOMAC Digest of Papers, March 1996, pp. 411-414.
- Foundry-Flexible ASIC Design for High-Performance Defence, Space, and Commercial Applications", 1996
- Bartholet, B.¹ Davis, S.² Russell, D.³ White, M.⁴

3
- 33747264999
- IEEE Nuc. and Space Rad. Effects Conf. Short Course, Indian Wells, CA, July 1996, pp. V-l - V-54.
- D. R. Alexander Design Issues for Radiation Tolerant Microcircuits for Space," 1996 IEEE Nuc. and Space Rad. Effects Conf. Short Course, Indian Wells, CA, July 1996, pp. V-l - V-54.
- Design Issues for Radiation Tolerant Microcircuits for Space," 1996
- Alexander, D.R.¹

4
- 0028727191
- Nuc. Sei. 41, 2229-22345 (1994).
- R. Velazco et al. "Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits," IEEE Trans. Nuc. Sei. 41, 2229-22345 (1994).
- "Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits," IEEE Trans.
- Velazco, R.¹

5
- 33747305633
- Proc. 3rd NASA Symp. on VLSI Design, Moscow, ID, October 1991, pp. 2. 3. 1-2. 3. 12.
- J. Canaris An SEU Immune Logic Family," Proc. 3rd NASA Symp. on VLSI Design, Moscow, ID, October 1991, pp. 2. 3. 1-2. 3. 12.
- An SEU Immune Logic Family,"
- Canaris, J.¹

6
- 0002901176
- IEEE Trans, on Nuc. Sei. , 39, 1679-1684(1992).
- M. N. Liu and S. Whitaker Low Power SEU Immune CMOS Memory Circuits," IEEE Trans, on Nuc. Sei. , 39, 1679-1684(1992).
- Low Power SEU Immune CMOS Memory Circuits,"
- Liu, M.N.¹ Whitaker, S.²

7
- 33747289854
- 1989, pp 150-152.
- T. P. Ma and P. V. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits: J. Wiley, 1989, pp 150-152.
- Ionizing Radiation Effects in MOS Devices and Circuits: J. Wiley
- Ma, T.P.¹ Dressendorfer, P.V.²

8
- 33747299071
- ASTM F996-92 Standard Test Method for Separating Ionizing Radiation-Induced MOSFET Threshold Voltage Shift into Components due to Oxide Trappped Holes and Interface States Using the Sub-Threshold Current-Voltage Characteristics," American Society for Testing and Materials, 1996.
- Standard Test Method for Separating Ionizing Radiation-Induced MOSFET Threshold Voltage Shift into Components Due to Oxide Trappped Holes and Interface States Using the Sub-Threshold Current-Voltage Characteristics," American Society for Testing and Materials, 1996.

9
- 33747315578
- Proceedings of the IEEE, Vol. 76, No. 1 1, Nov. 1988.
- L. R. Rockett, Jr. Designing Hardened Bulk/Epi CMOS Circuits", Proceedings of the IEEE, Vol. 76, No. 11, Nov. 1988.
- Designing Hardened Bulk/Epi CMOS Circuits"
- Rockett Jr., L.R.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.