Integrating a Boolean satisfiability checker and BDDs for combinational equivalence checking

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1998, Pages 222-225

  Gupta, Aarti ^a   Ashar, Pranav ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER SIMULATION; DECISION THEORY; EQUIVALENCE CLASSES; ITERATIVE METHODS; LOGIC DESIGN; LOGIC GATES;

AUTOMATIC TEST PATTERN GENERATION (ATPG); BINARY DECISION DIAGRAMS (BDD);

COMBINATORIAL CIRCUITS;

EID: 0031700823     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)